﻿<?xml version="1.0" encoding="utf-8"?>
<?xml-stylesheet type="text/xsl" href="thpdoc.xsl"?>
<page id="sizeof" suffix=" Function">
  <subsection>Returns the size of a vector type, vector variable, list or a generate foreach statement.</subsection>
  <code>int sizeof(any object);</code>
  <examples>
	<example name = "Vectors">
		<code>entity Test
{
	typedef logic[4] DataType;
	
	signal logic[8] test1;
	signal DataType test2;
	
	process dummy()
	{
		auto x = test1 cat test2;
		int a = sizeof(DataType);
		int b = sizeof(test1);
		int c = sizeof(test2);
		int d = sizeof(x);
	}
}</code>
Generated VHDL code:
<code>dummy : process  is
	variable x : std_logic_vector(11 downto 0);
	variable a : integer;
	variable b : integer;
	variable c : integer;
	variable d : integer;
begin
	x := (test1 &amp; test2);
	a := 4;
	b := 8;
	c := 4;
	d := 12;
end process dummy;</code>
	</example>
	<example name="Lists">
	<code>entity Test
{
	const any lst1 = (1, 2, 3);
	const any lst2 = (lst1, 4, 5);
	
	process dummy()
	{
		int a = sizeof(lst1);
		int b = sizeof(lst2);
	}
}</code>
	Generated VHDL code:
<code>dummy : process  is
	variable a : integer;
	variable b : integer;
begin
	a := 3;
	b := 5;
end process dummy;</code>
	</example>
	<example name="Generate foreach">
	<code>entity Test
{
	const any lst1 = (1, 2, 3);
	
	generate something foreach(any i in lst1)
	{
		signal logic[8] sig = i;
	}
	
	process dummy()
	{
		int a = sizeof(something);
	}
}</code>
	Generated VHDL code:
<code>entity Test is
end entity Test;

architecture Behavioral of Test is
	signal something_0_sig : std_logic_vector(7 downto 0) := X"01";
	signal something_1_sig : std_logic_vector(7 downto 0) := X"02";
	signal something_2_sig : std_logic_vector(7 downto 0) := X"03";
	
	begin
		a := 3;
		
end architecture Behavioral;</code>
	</example>
  </examples>
  <seealso id="generate"/>
  <seealso id="foreach"/>
  <seealso id="lists"/>
  <seealso id="typeof"/>
</page>