When used as a type name, the
entity Adder
{
port in logic[8] X, Y;
port out logic[8] Result;
Result = X + Y;
}
entity Testbench
{
Adder uut(
X = auto(0),
Y = 1,
Result = auto
);
process test()
{
uut.X += 3;
wait(10ns);
}
}
simulate_entity(Testbench);
The entity Testbench is
end entity Testbench;
architecture Behavioral of Testbench is
signal thp_uut_autosig_X : std_logic_vector(7 downto 0) := X"00";
signal thp_uut_autosig_Result : std_logic_vector(7 downto 0);
component Adder is
Port (
X : in std_logic_vector(7 downto 0);
Y : in std_logic_vector(7 downto 0);
Result : out std_logic_vector(7 downto 0)
);
end component Adder;
begin
uut : Adder
port map (
X => thp_uut_autosig_X,
Y => X"01",
Result => thp_uut_autosig_Result
);
test : process is
begin
thp_uut_autosig_X <= (thp_uut_autosig_X + X"03");
wait for 10ns;
end process test;
end architecture Behavioral;
signal logic[8] a, b, c;
process test (clk.rising)
{
auto tmp = a cat b;
c = tmp[12 to 5];
}
Generated VHDL code:
test : process (clk) is
variable tmp : std_logic_vector(15 downto 0);
begin
if rising_edge(clk) then
tmp := (a & b);
c <= tmp(12 downto 5);
end if;
end process test;
The type of the variable "tmp" has been derived from the "a cat b" expression.