logic[] __hex(string value);
The Note that you can initialize vectors of size 32 and less with normal C++ style integral constants (e.g. 15, 0xF or 0b1111).
entity Test
{
signal auto xxx = __hex("010"), yyy = 0x010;
signal logic[12] xx2 = __hex("010"), yy2 = 0x010;
}
Generated VHDL code:
signal xxx : std_logic_vector(11 downto 0) := X"010";
signal yyy : integer := 16;
signal xx2 : std_logic_vector(11 downto 0) := X"010";
signal yy2 : std_logic_vector(11 downto 0) := X"010";