What is VisualHDL?
VisualHDL is an integrated development environment (IDE) rapid design for FPGAs. It is based on THDL++ - a C++-like language with fully paralell VHDL semantics. It allows developing fully parallel FPGA designs having the flexibility, modularity and maintainability of C++ code. The IDE supports code completion, code navigation, design visualization and tons of other useful features. The IDE is fully integrated with Xilinx ISE toolchain. Moreover, a command-line THDL++-to-VHDL compiler can be used in conjunction with any other tool, that supports VHDL.
Is it a C++-to-FPGA compiler?
No, VisualHDL is a new-generation tool. Instead of converting the inherently sequential C++ code into fully parallel VHDL synthesizable for FPGAs, VisualHDL brings the productivity of C++ and C++ IDEs to the FPGA world. The THDL++ language provides a C++-like syntax, supports object-oriented features, templates, inheritance and reflection, while being fully parallel by design. We use VisualHDL internally for designing highly flexible FPGA IP cores for our customers.
The source code has been released under the LGPL license. You can get it from SourceForge SVN:
You can watch a short video showing some features of VisualHDL below. It is recommended to turn on fullscreen mode.